Chip Development
Our group is developing full custom chips since 1994. Up to now, more than 40 designs have been submitted and successfully tested. They cover the field from simple transistor test structures to full readout chips for silicon strip, hybrid- and depleted monolithic pixel detectors using a wide variety of CMOS technologies. Further down this page lists the designs starting with the most recent submissions.
Chip developments sorted by project
(major developments only)
ATLAS Pixel Detector
ITkPixV1
RD53A
FE65_P2
CDR_CML
FE-4B
FE-4A
LVDSTrans
FE-TC4
FE-C4P3B
FE-C4P3C
FE-CP1
FE-I4Proto1
FE-I3
FE-I2
FE-I1
ATLAS CMOS Pixel Detector
TJ_MONOPIX
LF_MONOPIX01
LF_CPIX
CCPD_LF
Belle II Pixel Detector - PXD (DEPFET)
DHPT 1.1 (65nm TSMC)
DHPT 1.0 (65nm TSMC)
DHPT 0.2 (65nm TSMC)
DHPT 0.1 (65nm TSMC)
DHP 0.2 (90nm IBM)
DHP 0.1 (90nm, IBM)
Depleted Monolithic Active Pixel Detectors (DMAPS/Smart Pixels)
Gaseous Pixel Detector
XFEL Pixel Detector
Medical X-ray
Other
ITkPixV1 - Full-scale Prototype Readout Chip for ATLAS
Submitted 3/2020, TSMC 65nm (RD53 collaboration)
ITkPix V1 is the first full-scale prototype readout chip for the ATLAS experiment at the upcoming HL-LHC. The chip is based on RD53A, measures 20 x 21 mm² and the pixel matrix contains 400 columns x 384 rows with a pixel pitch of 50 µm x 50 µm. Compared to its predecessor, ITkPix V1 uses one analog front end type across the whole pixel matrix and incorporates several new features and improvements. The next iteration ITkPix V2 is currently being designed and will be
submitted in 2022.
TJ_MONOPIX - Monolithic CMOS Pixel Demonstrator for the outer ATLAS pixel layers
Submitted 10/2017, TowerJazz 180 nm (Bonn, CERN)
TJ MonoPix
is a large-scale (18 x 10 mm²) depleted monolithic active pixel sensor (DMAPS) demonstrator
in a modified 180 nm CMOS process on a high resistivity substrate.
The 224 x
448 pixel matrix has a pitch of 36.4 x 40 µm² and is optimized for low sensor
capacitance to reduce noise and analog power. The small collection electrodes
are placed outside of the deep p-well (small fill-factor).
Characterization
measurements started in 01/2018.
RD53A - Readout Chip Prototype for ATLAS and CMS
Submitted 8/2017, TSMC 65nm (RD53 collaboration)
RD53A is a
large scale prototype (400 columns x 192 rows, ~2 x 1 cm², 50 µm x 50 µm pixel
pitch, 500 M transistors), to demonstrate radiation tolerance and high hit rate
capabilities, as required for the innermost layers of ATLAS and CMS after the
HL-LHC upgrades.
The chip contains
three different analog front-end designs for performance comparison, a
Shunt-LDO for serial powering and a fast data link with up to 4x 1.28 Gbit/s.
The characterization of RD53A started in
12/2017. The second iteration RD53B is currently being designed and will be
submitted in the second half of 2019.
LF_MONOPIX01 - Monolithic CMOS Pixel Detector Prototype for ATLAS
Submitted 10/2016, LFoundry 150nm (CPPM, IRFU, BN)
First prototype of a fully monolithic pixel chip for the outer layers of the ATLAS pixel detector. The 1 cm x 1 cm matrix has a pixel size of 50 µm x 250 µm and and implements a fast column-drain readout similar to the architecture of the FE-I3 pixel chip. The analog FE design is based on the structures from LF_CPIX. The CMOS process is using a 2 kOhm cm substrate material which will be thinned to 100 µm - 300 µm thicknesses and thus can be fully depleted.
LF_CPIX01 - Active CMOS Pixel Detector Prototype for ATLAS
Submitted 8/2016, LFoundry 150nm, (CPPM, IRFU, BN)
This is the LF prototype chip designed for the initial ATLAS CMOS demonstrator program. The pixel matrix has a size of 1 cm x 1 cm and a pixel size of 50 µm x 250 µm compatible for bump bonding to FE-I4. There are passive pixels (for reference) and active pixels which could be ac- or dc-coupled to the FE-I4 chip. The CMOS process is using a 2 kOhm cm substrate material which will be thinned to 100 µm - 300 µm thicknesses and thus can be fully depleted.
FE65_P2 - 65nm Prototype Matrix Chip 
Submitted 10/2015, TSMC 65nm
This pixel matrix chip is the first prototype developed within the context of the RD53 collaboration, which aims at developing pixel chips in a 65nm CMOS technology for HL-LHC upgrades of ATLAS and CMS pixel detectors. This prototype chip has a 64 x 64 pixel matrix with 50 µm pixel pitch. The chip was designed with a digital design flow having analog islands (the analog pixel fronentds) in a see of digital cells.
LFB01 Test Chip
Submitted 8/2014, LFoundry 150nm
The LFB01
submission covered five independent designs: two versions of an active
pixel sensor to be connected to FE-I4 (CCPD_LF, versions A and B), a 32 x
64 pixel matrix with 50x50µm2 pixel size based on a current
mode read-out, a passive pixel matrix for FE-I4, and a pixel sensor
array for low energy X-ray spectroscopy applications. The production of
the LFB01 chip is using high resistive (2 kOhm cm) p-type bulk wafers
which are to be thinned down to 100 - 200 µm and processed for a
backside contact.
Shown on the right side are the CCPD_LF design, the
passive planar pixel sensor for FE-I4 and the current mode pixel matrix
(from top to bottom).
DMAPS Prototype TSB01 
Submitted 8/2013, Toshiba 130nm
This DMAPS prototype chip was developed using a standard 130nm CMOS technology using a high resitivity bulk material (4-5 kOhm cm). Three different pixel matrices with various charge collecting structures were implemented. The use of a multi layer mask set for the production of the TSB01 chip allows to have access to full wafers at reduced costs.
DHPT 1.0 / DHPT 1.1 / DHPT 1.2(b)
Submitted 8/2013 and 9/2015, TSMC 65nm
First (1.0) and updated (1.1, 1.2, 1.2b) production version of the full size Data Handling Processor for the DEPFET Vertex Detector PXD in the Belle 2 experiment.
- 12 mm2
- 296 bumps
- 3Mbit memory
- pedestal correction & zero supression
- 1.6 GHz data link
DMAPS Prototype XTB01
Submitted 3/2013, XFAB 180nm
The XTB01 is the implementation of a monolithic active pixel sensor (MAPS) based on a high voltage silicon-on-insulator technology (HV-SOI) from XFAB. This technology has contacts thru the buried oxide layer (BOX) and allows implants on the handle wafer which enables the implementation of the charge collecting diodes. A major improvement compared to other standard SOI technologies which have been used so far for MAPS developments is an additional non-depleted implant between the BOX and the active device layer which improves the radiation hardness considerably (no back gate effect due to TID induced charge-up of the BOX layer).
DMAPS Prototype Pegasus
Submitted 2/2013, TowerJAZZ 180nm
In this process technology an additional deep p-well allows the use of PMOS transistors in the active pixel region without compromising the charge collection. The chip production was done using different substrate materials (bulk and epi-layer wafers). The Pegasus chip has four different matrices with 25 x 25 µm2 pixel size with either 3T or CSA read-out. The design has been done in cooperation with IPHC Stasbourg.
DMAPS Prototypes EPCB01 and EPCB02
Submitted 10/2012 and 4/2014, ESPROS 150nm
A first DMAPS test chip was designed using a 150nm CMOS technology based on 2k Ohm cm high resistive silicon substrate thinned down to 50µm. Six different pixel arrays of the DMAPS pixels have been integrated in the EPCB01, differing by architecture of the FE electronics, sensor biasing, sensor coupling and geometry of the sensitive elements. The second prototype chip EPCB02 was submitted with a similar matrix configuration as EPCB01 but with improved charge collection node layout and optimized charge sensitive amplifier performance.
DHPT 0.2
Submitted 3/2012, TSMC 65n
Test structures for future ATLAS and DEPFET projects.
- LVDS IO
- 8-bit, 10 Msps ADC
- Analog Pixel Front-end
- Temperature sensor (U Barcelona
DHPT 0.1
Submitted 10/2011, TSMC 65nm
Test structures for future ATLAS and DEPFET projects.
- PLL + GBit link driver
- Charge sensitive amplifier
- Memory test structures
- DAC, current reference (U Barcelona)
FE-I4B
Submitted 10/2011, IBM 130nm
Readout chip for the ATLAS hybrid pixel detector insertable B-layer (IBL), ~80 Million transistors
Gossipo4
Submitted 08/2011, IBM 130nm
demonstrator of a front-end chip design for TimePix3 designed in collaboration with CERN and Nikhef (Amsterdam)
DHP 0.2
Submitted 07/2011
Second prototype of the PXD data handling processor (full chip). Features: 1.6 GHz PLL, Gigabit driver with programmable pre-emphasis, on-chip bias DACs
PixCap
Submitted 06/2011, LFoundry 150nm
Capacitance measurement chip designed for measuring parasitic capacitance of ATLAS pixel sensors.
- Array of 8x40 programmable charge pumps
- Integrated test capacitors
LvdsTrans
Submitted 11/2010, IBM 130nm
8 channel LVDS transceiver chip with integrated reference and biasing structure
DHP 0.1
Submitted 03/2010, IBM 90nm
Halve size prototype chip for the Belle II pixel vertex detector (PXD) data handling processor. Features: 1.6 GHz PLL, Gbit link, memories, analog test structures, 200µm pitch bump bonds
FE-I4A
Submitted 07/2010, IBM 130nm
Readout chip for the ATLAS hybrid pixel detector upgrade, full size prototype, ~80 Million transistors
FE-TC4
Submitted 04/2010, Chrt 130nm
Chartered - Tezzaron 3D version of FE-14 prototype readout chip designed for the ATLAS hybrid pixeldetector.
FE-C4_P3B
Submitted 11/2009, Chrt 130nm
Chartered 2D version of FE-14 designblocks:
10 bit DAC and Pulsgenerator
FE-C4_P3C
Submitted 11/2009, Chrt 130nm
Chartered 2D version of FE-14 designblocks:
PLL and pads with LVDS driver/ receiver included
Gossipo3
Submitted 09/2009, IBM130nm
demonstrator of a front-end chip design for the readout of Micro-Pattern Gas Detectors designed in collaboration with Nikhef (Amsterdam)
Hpad01
Submitted 03/2009, IBM 130nm
Test structures consisting of capacitors and switches used as analog memory cells in the XFEL readout chip
Fulldiff2
Submitted 03/2009, UMC 180nm
10 pixel with full differential readout channel consisting of CSA, comparator and counter
TurboPll
Submitted 03/2009, IBM 130nm
640 MHz Pll, Shunt-LDO Regulator, I2C Slave, HPad Test structures, transistors to study the shifting of the threshold voltage and the bulk effect caused by radiation influences.
Compton2
Submitted 03/2009, AMS 350nm
stripdetector readout chip with 128 channels. Use transconductance amplifier in the Feedback.
FEC_P1
Submitted 02/2009, Chrt 130nm
Chartered 2D version of FE-14 prototype readout chip designed for the ATLAS hybrid pixeldetector.
Testarkis2
Submitted 01/2009, UMC 180nm
full differential charge sensitive amplifiers with two stages for the differential readout of 3D Sensors
Shuldo
Submitted 07/2008, IBM 130nm
Shunt - LDO Regulator, Low-ESR LDO Regulator. 10 Bit DAC, Tristate LVDS driver
TCChip
Submitted 03/2008, IBM 130nm
4 channel LVDS transceiver chip
FEI4-Proto1
Submitted 03/2008, IBM 130nm
prototype of the FE-I4 readout chip used for hybrid pixel detector in the ALTLAS experiment.
FullDiff
Submitted 10/2007, UMC 180nm
10 ch. pixel front-end chip with fully differential signal processing.
LVDS
Submitted 07/2007, UMC 130nm
Test chip with LVDS transmitter and receivers blocks.
Testakis
Submitted 02/2007, UMC 180nm
Test chip containing: 8 Bit DAC, 10 Bit DAC, low-voltage bandgap reference, 100 MHz voltage buffer, transimpedance amplifier, fully differential CSA
xTalk
Submitted 10/2006 , UMC 180nm
Test chip to study the influence of various guard structures on cross-talk.
CIX 0.2
Submitted 04/2005, AMS 0.35 µm.
Size: 23.3 mm², 295.000 transistors.
Second generation prototype ASIC for x-ray imaging using simultaneous photon counting and charge integrating readout.
CIX 0.19
submitted 03/2005, AMS 0.35 µm
Size: 2.4 mm²
This chip incorporates several structures in differential-current-mode logic as well as an LVDS output stage.It was used for some detailed measurements for CIX0.2
Compton(Abacus)
submitted 03/2005, AMS 0.35 µm
Size: 20.4 mm²
128 channel counting readout ASIC for a sillicon strip detector used in a Compton polarimeter. Each channel has a CSA with continuous reset, pole-zero cancellation, CR-RC shaper with variable shaping time from 100ns to 400ns, a comparator with a DAC to tune the comparator threshold and an asynchronous ripple counter
CURO2
Submitted 09/2003 to TSMC 0.25 µm.
Size: 20.3 mm²
CUrrent Read Out chip for a DEPFET silicon detector matrix. CURO2 performs the parallel readout of 128 channels. For every readout channel a regulated cascode input stage and a current memory cell is used. Hits are found by a comparison with a programmable threshold current.
CIX
Submitted 08/2003 to AMS 0.35 µm.
Size: 6.3 mm², 30530 transistors.
Test chip for x-ray imaging applaying a circuit architecture that allows simultaneous counting and integrating readout.
CMOS-Matrix
Submitted 04/2003 to AMS 0.35 µm.
Size: 23.0 mm², 65540 transistors.
CMOS based pixel chip that is used to test a complete DEPFET readout system. The CMOS-Matrix has 64x128 cells with every cell having a NWELL-PSUB photodiode and additional circuitry that generates an offset current and an illumination dependent current.
Switcher2
Submitted 09/2002 to AMS 0.8 µm HV.
Size: 22.0 mm², 21220 transistors.
The SWITCHER2 chip is a 2x64 channel high voltage multiplexer used to control the readout of a DEPFET silicon detector. A RAM on the chip is used to store the control sequence. Several chips can be daisy chained if more than 64 channels are to be addressed.
SILAB1B
Submitted 01/2002 to TSMC 0.25 µm.
Size: 5.77 mm², 58000 transistors.
Test chip for the DEPFET based vertex detector for TESLA. It includes high speed current sampling structures, a hit scanner and a current comparator.Care was taken in the design of the on-chip control logic to allow simple testing of the various blocks at high speed.
SILAB1A
Submitted 01/2002 to TSMC 0.25 µm.
Size: 5.28 mm², 18000 transistors.
This test chip contains several structures to measure transfer characteristics, capacitances and matching of PMOS and NMOS devices with different geometries. Functional blocks include logic test circuits and a charge sensitive preamplifier with feedback.
FE-I
Submitted 11/2001 to IBM 0.25 µm.
Size: 81.4 mm², 2450000 transistors.
Front
end chip for the Atlas pixel detector, in collaboration with LBL
Berkeley and CPPM Marseille. The chip consists of an array of
18x160 pixels of 400x50mm² size. Each pixel contains a charge
sensitive amplifier, a discriminator with adjustable threshold and
a digital time stamp readout. The hit data is buffered at the bottom
of the chip until a trigger signal selects or discards them.
FAUST12
Submitted 8/99 to AMS 0.8 µm.
Size: 4.8 mm², 3100 transistors.
Analog test amplifiers for pixel readout and other test structures.
FE-D
Submitted 8/98 to DMILL 0.8 µm, BiCMOS.
Size: 81.4 mm², 730000 transistors.
Front end chip for the Atlas pixel detector, in collaboration with CPPM Marseille and LBL Berkeley.
FAUST11
Submitted 7/98 to AMS 0.8 µm.
Size: 6.1 mm², 2400 transistors.
Analog
test circuits like voltage references, a charge pump, buffer
amplifiers, charge sensitive amplifiers, discriminators.
FE-C
Submitted 4/98 to AMS 0.8 µm.
Size: 81.4 mm², 892000 transistors.
FE-A (PIRATE)
Submitted 10/97 to AMS 0.8 µm, BiCMOS.
Size: 81.4 mm², 880000 transistors.
Pixel
readout chips for ATLAS with full data sparsification logic in
collaboration with CPPM Marseille. The second submission FEC is
very similar to FEA but does not need the bipolar transistor.
CARLOS2.0
Submitted 7/01 to AMS 0.8 µm.
Size: 16.2 mm², 140000 transistors.
CARLOS1.1
Submitted 7/98 to AMS 0.8 µm.
Size: 6.5 mm², 4400 transistors.
CARLOS1.0
Submitted 12/97 to AMS 0.8 µm.
Size: 5.9 mm², 700 transistors.
A
64 channel low noise current to current amplifier for pulsed
clear DEPJFET matrix (64x64 pixel) with track and hold and one
fast serial output.
SWITCHER 1.1
Submitted 7/99 to AMS 2.0 µm, HVCMOS.
Size: 23.8 mm².
SWITCHER 1.0
Submitted 3/97 to AMS 2.0 µm, HVCMOS.
Size: 23.8 mm².
A 64 channel high voltage output chip to select and/or clear a single row of a pulsed clear DEPFET matrix.
Submitted 9/00 to AMS 0.8 µm.
Size: 41.6 mm², 429000 transistors.
MPEC2.1
Submitted 8/99 to AMS 0.8 µm.
Size: 48.7 mm², 400000 transistors.
MPEC2.0
Submitted 11/98 to AMS 0.8 µm.
Size: 14 mm², 59000 transistors.
MPEC1D
Submitted 6/98 to AMS 0.8 µm.
Size: 23.2 mm², 159000 transistors.
MPEC1.0
Submitted 2/97 to AMS 0.8 µm.
Size: 22.1 mm², 147000 transistors.
These are counting pixel readout chip for imaging applications.
FAUST10.1
Size: 20.5 mm², 26600 transistors.
FAUST10.0
Submitted 4/96 to Mietec 2.0 µm.
Size: 19 mm², 6850 transistors.
A
programable 128 channel multiplexer to read out silicon strip
front end chips in applications without external trigger signals.
MEPHISTO
Submitted 6/96 to AMS 0.8 µm.
Size: 11 mm², 61000 transistors.
A
prototype of a digital 128 channel front end chip for silicon
strip detectors with real time data sparsification and on chip
data buffering.
BIER51
Submitted 4/96 to AMS 0.8 µm, BiCMOS.
Size: 30 mm², 150000 transistors.
A pixel readout chip for ATLAS in collaboration with CPPMarseille.
FAUST7
A 128 channel counter which uses linear feedback shift registers as counting elements. More info can be found in the paper 'An area efficient 128 channel counter chip'.
FAUST6
A readout buffer for the continuous DEPJFET detector.
The second image shows the needle test of FAUST6 on a probe station.
FAUST4
A self adjusting delay circuit (tunedelay) for use in pixel readout chips. Results can be found in the paper by P.Fischer and A. Joens: 'A self adjustment technique minimizing channel to channel variations in VLSI readout chips'.
FAUST2
Submitted to Mietec 2.4µm.
An analog four quadrant multiplier for use in a readout chip for silicon strip detectors.
FAUST1b
Submitted to Mietec 2.4µm.
Simple test structures (transistors, current mirrors, differential pair, etc...). They have been characterized in great detail in order to verify the simulations and to test different transistor models. Some results can be found in the Thesis of Andrea Jöns who was our first student doing chip design.
FAUST1a
Submitted to Mietec 2.4µm.
A pseudo random noise generator done in standard cell design. This was the first design we submitted after having installed the cadence software. The fully synchronous design operates correctly at a frequency of 60 MHz.
