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DMAPS (Depleted Monolithic Active Pixel Sensors)

Monolithic Active Pixel Sensors (MAPS) have been proposed and developed since the late 1990ies using substrate wafers with an epitaxial (epi) layer (thickness 10-15 µm) underneath a standard CMOS electronics layer, in which charge can be collected at an (n-type) collection electrode, albeit by unordered and slow diffusion rather than by drift in a directed electric field. These detectors can become very thin (~50µm) resulting in a material budget an order of magnitude below that of hybrid pixel detectors. Due to the thin depleted epi-layer and often incomplete charge collection the signal is however tiny (~1000 e). In addition, the readout is comparatively slow resulting in small readout frame rates, and the radiation tolerance is factors of 100 – 1000 below that required at the LHC. Finally, for X-ray detection the absorption probability in the thin epitaxial layer is too small to be efficient.

The DMAPS concept is based on the idea of monolithic active pixels, however it combines it with the fast and efficient charge collection provided by a depleted bulk. To achieve this feature, detector grade wafer material, made out of high resistivity silicon, has to be used in a standard CMOS fabrication process. The DFG project 'DMAPS' has the goal to evaluate different CMOS vendors which would allow the use of high resistivity, and thus fully depletable, sensor material. Despite of the charge collection by drift, which leads to a fast collection process, the complexity of the signal processing inside the pixel cell is another key parameter of this detector concept. To achieve this, full CMOS electronics (meaning PMOS and NMOS transistors) has to be used. This poses additional requirements on the CMOS technology (i.e. multiple nested well implantations), to be able to isolate both transistor polarities form the charge collection process.

 

crosssection_dmaps

Cross section of DMAPS pixel cells. Charge collection with a deep n-well with the electronics inside (left), low capacitance charge collection with a small n-implant and the electronics inside a deep p-well (right).

 

First DMAPS Test Chip (EPCB01)

A first DMAPS test chip was designed using a 150nm CMOS technology on 2k Ohm cm high resistive silicon substrate thinned down to 50µm (ESPROS technology). Six different pixel arrays of the DMAPS pixels have been integrated in the EPCB01, differing by architecture of the FE electronics, sensor biasing, sensor coupling and geometry of the sensitive elements.

micrograph_pixel

Micrograph of the wire-bonded EPCB01 fully depletable monolithic pixel chip.

 

In the meanwhile the DMAPS concept also has been implemented with other techologies with various silicon materials, CMOS process options, and readout configuration:

Depleted Monolithic Active Pixel Detectors Prototype chips (DMAPS/Smart Pixels)

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