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PXD - Pixel Vertex Detector for Belle II


With the planned upgrade of the KEK-B factory to increase the luminosity of the e+ e- collider up to 8 x 1035 cm-2s-1, also the Belle detector will be re-designed (Belle II). In particular the Belle vertex detector, which currently consists of four layers of double sided micro-strip detectors (SVD), will be upgraded with the insertion of two additional layers of pixel detectors (PXD) which are needed to cope with the higher track densities.
The layout of the Belle II pixel detector foresees two layers at 1.8 cm and 2.2 cm radius respectively. The beam pipe will have a radius of approx. 1.6 cm. The cylindrical barrels will be constructed from 8 (layer 1) and 12 modules (layer 2). Due to the asymmetric beam energies, the detector will have different acceptance regions in forward and backward direction. Some of the main specifications of the PXD are given in table below.


Figure 1. Mechanical mockup of the PXD


Table 1. PXD specifications

Number of pixels per module 250 x 1536
Pixel size (r-phi, z) 50µm x (60-75) µm
Frame time 20 µs
Material budget per layer 0.15% X0
Resolution (r-phi, z) <10µm, < 20µm
Occupancy at 1.8 cm radius 0.2 hits µm-2s-1
Radiation environment ~1 Mrad/year


PXD Module

The proposed two layer vertex detector consists of 'all-silicon' modules: The read-out and control ASICs will be bump bonded on the rigid edges of the DEPFET substrate whereas in the region of the active pixel matrix the substrate will be thinned down to 75 µm. The front-end electronics is subdivided in three different ASIC types: One chip will provide up to 20 V output swing for the control voltages of the DEPFET matrix (SWITCHER), the current signals are being digitized by a multichannel ADC chip (DCD) and the processing of the digital data and module control functionality is implemented in a data handling chip (DHP) described below.





Figure 2. Sketch of an "all-silicon" DEPFET module. The light gray area is the active pixel region which is thinned down to 75 µm, the dark gray region (balcony and end-of-stave) is rigid to support the bump bonding of the chips.




Figure 3: Image of a 36x9.6mm² DEPFET Prototype Matrix (PXD6) with 92160 pixel and bump bonded ASICs. On the bottom there are 4 Switcher ASICs for row selection, on the right side are three DCD DHP ASIC pairs, the rightmost is the DHP.


Data Handling Processor - DHP

The data handling processor will be used to reduce the data rates produced by the DCD chips. This is achieved by zero-suppressing the DCD data and the read-out of triggered data only. To allow efficient zero-suppression the raw data has to be corrected for common mode noise and fixed pattern signals (pedestals). After that a hit finding logic will select the signal data form hit pixels and the data is transfered to the back-end electronics via gigabit data links.


Figure 4. Flip-chip assembly of a DHPT1.0. The silicon adapter provides wire bond connection for protoype testing and allows the flipchip of an additional DCDB ASIC.


The DHP chip development started in our group in 2009. The first two prototype chips were produced in a 90nm technology (DHP 0.1 and DHP 0.2). Recently the porting of the design to a 65nm technology has been done. After successfully prototyping the full custom analog blocks with two test chips (DHPT 0.1 and DHPT 0.2) the first full size DHP chip in 65nm technology (DHPT 1.0) has been designed and submitted in Sep 2013.


Figure 5. Layout of the full scale DHP 1.0 submitted in September 2013 (TSMC 65nm). The chip has a size of ~3 mm x 4 mm and 296 bump bonds.


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